Circuit Design and Simulation with VHDL programming assignment help

Solution.pdf

Say that s1 to s4 are four VHDL signals. Based on the assignments below, list which syn- thesizable predefined data types each of these signals can belong to. 

s1 <= '0'; s2 <= 'Z'; s3 <= TRUE; s4 <= "01000"; 

Exercise 3.2: Possible Data Types C2 

Say that s1 to s4 below are another four VHDL signals. Based on the assignments pre- sented, list which synthesizable predefined data types each of them can belong to. 

s1 <= "0100Z"; s2 <= ('0','1','0','0', '0'); s3 <= (OTHERS => 'Z'); s4 <= 255; 

Exercise 3.10: Subtypes 

Consider the predefined data types INTEGER and STD_LOGIC_VECTOR. Consider also the two user-defined types below. For each, write a possible SUBTYPE. 

TYPE oneDoneD IS ARRAY (POSITIVE RANGE <>) OF INTEGER; TYPE twoD IS ARRAY (POSITIVE RANGE <>, 3 DOWNTO 0) OF BOOLEAN; 

Exercise 3.15: 1DD1D Array Examples 

Consider the 1D x 1D array shown in figure 3.2c. Write three examples of possible array types that fall in that category (one example is already included below; complete the list with type2 and type3). 

TYPE type1 IS ARRAY (NATURAL RANGE <>) OF BIT_VECTOR(7 DOWNTO 0); 

Exercise 3.16: 2D Array Examples 

Consider the 2D array shown in figure 3.2d. Write three examples of possible array types that fall in that category (one example is already included below; complete the list with type2 and type3). 

TYPE type1 IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; 

Exercise 3.17: 1DD1DD1D Array Examples 

Consider the 1D x 1D x 1D array shown in figure 3.2e. Write three examples of possible array types that fall in that category (one example is already included below; complete the list with type2 and type3). 

TYPE matrix IS ARRAY (1 TO 4) OF BIT_VECTOR(7 DOWNTO 0); TYPE type1 IS ARRAY (NATURAL RANGE <>) OF matrix; 

Exercise 3.19: Type Conversion by Type Casting 

Write a line of VHDL code that makes a conversion using type casting for each type con- version listed below. In each case, indicate the package(s) (if any) that must be declared in the code for the conversion to be valid. 

a) From STD_LOGIC_VECTOR to UNSIGNED. b) From SIGNED to STD_LOGIC_VECTOR. 

Exercise 3.20: Type Conversion by Specific Functions 

Write a line of VHDL code that converts the types below using type-conversion functions. In each case, write as many options as possible, always indicating the package of origin of the function being used. 

a) From INTEGER to STD_LOGIC_VECTOR; b) From BIT_VECTOR to STD_LOGIC_VECTOR; c) From STD_LOGIC_VECTOR to UNSIGNED; d) From STD_LOGIC_VECTOR to INTEGER; e) From SIGNED to STD_LOGIC_VECTOR. 

Exercise 3.22: Array Slices 

Say that figures 3.2b to 3.2d represent the signals s1(3:0), s2(1:3)(3:0), and s3(1:3, 3:0), respectively. Write the values corresponding to each slice below (the first one was already answered). 

a) s1(3 DOWNTO 1): "010" b) s1(2): c) s1: d) s2(3)(1 DOWNTO 0): e) s2(1): f) s3(2, 2): 

Exercise 3.23: Array Dimensionality 

What is the dimensionality (scalar, 1D, 1D x 1D, 2D, etc.) of each signal and variable above based on the number of bits (figure 3.2)? 

---------------------------------------- SIGNAL s1: BIT; SIGNAL s2: BIT_VECTOR(7 DOWNTO 0); SIGNAL s3: STD_LOGIC; SIGNAL s4: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL s5: INTEGER RANGE -35 TO 35; VARIABLE v1: BIT_VECTOR(7 DOWNTO 0); VARIABLE v2: INTEGER RANGE -35 TO 35; ---------------------------------------- 

The signals and variables below are for exercises 3.23 to 3.27. 

---------------------------------------- SIGNAL s1: BIT; SIGNAL s2: BIT_VECTOR(7 DOWNTO 0); SIGNAL s3: STD_LOGIC; SIGNAL s4: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL s5: INTEGER RANGE -35 TO 35; VARIABLE v1: BIT_VECTOR(7 DOWNTO 0); VARIABLE v2: INTEGER RANGE -35 TO 35; ---------------------------------------- 

Exercise 3.26: Illegal Assignments C1 

Explain why the assignments below are illegal (see main causes of mistakes in section 3.19). 

a) s1(0) <= s2(0); 

b) s3 <= s1 OR s2(2); c) s2 <= (8=>'0', OTHERS=>'Z'); 

d) v2 <= -35; 

Exercise 3.27: Illegal Assignments C2 

Explain why the assignments below are illegal (see main causes of mistakes in section 3.19). 

a) s3 := 'Z'; b) s2(7 DOWNTO 5) <= v1(3 DONWTO 0) OR "1000"; 

c) v1(7) <= s1 AND s2(0); d) s4(0) <= s2(0); 

The signals and their types below are for exercises 3.29 to 3.30. 

s1 –> TYPE type1 IS ARRAY (7 DOWNTO 0) OF BOOLEAN; s2 –> TYPE type2 IS ARRAY (7 DOWNTO 0) OF BIT; s3 –> TYPE type3 IS ARRAY (1 TO 4) OF INTEGER RANGE -128 TO 127; s4 –> TYPE type4 IS ARRAY (NATURAL RANGE <>) OF BIT_VECTOR(7 DOWNTO 0); s5 –> TYPE type5 IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; s6 –> TYPE type6 IS ARRAY (1 TO 4) OF type4; s7 –> TYPE type7 IS ARRAY (1 TO 4, 1 TO 4, 1 TO 4) OF STD_LOGIC; 

Exercise 3.29: Legal versus Illegal Array Slices 

For each slice below, respond: to which case in figure 3.7 does it correspond? (Note that not all are represented in figure 3.7, so make a sketch for the missing ones.) Why are the first ten supported while the last five might not be? 

a) s1(1) 

b) s2(6 DOWNTO 1) c) s3(4) d) s4(0) 

e) s4(1)(5 DOWNTO 3) f) s4(2)(1) g) s5(0,0) h) s6(1)(0) i) s6(2)(0)(7 DOWNTO 5) j) s6(3)(0)(7) k) s4(0 TO 1)(7) 

l) s5(1 TO 3, 3) m) s5(1 TO 2, 1 TO 2) 

n) s5(0, 2 TO 3) o) s5 (0 TO 1, 0 TO 1, 0 TO 1) 

Exercise 3.30: Illegal Assignments C3 

Explain why the assignments below are illegal (see main causes of mistakes in section 3.19). 

a) s4(0)(0) <= s7(1,1,1); b) s6(1) <= s4(1); 

c) s1 <= "00000000"; 

d) s7(0)(0)(0) <= 'Z'; 

e) s2(7 DOWNTO 5) <= s1(2 DOWNTO 0); f) s4(1) <= (OTHERS => 'Z'); g) s6(1,1) <= s2; 

h) s2 <= s3(1) AND s4(1); i) s1(0 TO 1) <= (FALSE, FALSE); 

j) s3(1) <= (3, 35, -8, 97);

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