Characteristics	LS TTL	ALS TTL	CMOS	HCMOS
VIL	0.8 V	0.8 V	1.5 V	1.0 V
VIH	2.0 V	2.0 V	3.5 V	3.5 V
IIL	0.4 mA	0.1 mA	1 uA	1 uA
IIH	20 uA	20 uA	1 uA	1 uA
VOL	0.5 V	0.5 V	0.5 V	0.1 V
VOH	2.7 V	2.75 V	4.5 V	4.9 V
IOL	8 mA	8 mA	0.4 mA	4 mA
IOH	0.4 mA	0.4 mA	0.4 mA	4 mA
Fan-out	20	20	10	20
Noise Margin	0.3 V	0.3 V	VNH=1.4 V VNL=1.4 V	VNH=1.4 V VNL=0.9 V

 

1. Definition of the terms Fan-out and Noise Margin.

Fan-out –

 

The Fan-out is a term which defines maximum number of digital inputs that output of a single logic gate can provide. The most of the TTL gates can provide up to 10 other digital gate or device. So, the TTL gate is having fan-out of 10. (Definition of fan-out, 2017)

Noise Margin –

 

The Noise margin can be defined as the amount of noise that CMOS circuit can resist without any compromise in the working of the circuit. The Noise margin ensures that a signal that is logic ‘1’ with a definite noise added to it, is accepted as logic ‘1’ and not as logic’0’. This is mainly the distinction between value of signal and noise value. (VLSI System Design - An IIT Alumnus Initiative.)

The noise margin can be defined as –

TASK 2: (LO4.2a & LO4.3a)

 

A circuit whose output is HIGH when the inputs are –

A is high and B is low and either input C or input D is also HIGH.

 

1. The Boolean expression that describes the performance of the required circuit,

The Boolean expression

 

1. The expression in Sum-of-Products (SOP) form –

The SOP form

 

This can be easily get by the truth table –

 

Input A	B	C	D	Output (Y)
0	0	0	0	0
0	0	0	1	0
0	0	1	0	0
0	0	1	1	0
0	1	0	0	0
0	1	0	1	0
0	1	1	0	0
0	1	1	1	0
1	0	0	0	0
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	0
1	1	0	1	0
1	1	1	0	0
1	1	1	1	0

 

 

The k-map,

0	0	0	0
0	0	0	0
0	0	0	0
0	1	1	1

 

 

1. By simulation software, we draw circuit diagram and simulate its operation,

 

The circuit schematic –

The output waveform –

Case A)

A=1,    B=0,    C=0,    D=1

Case B)

A=1,    B=0,    C=1,    D=0

Case C)

A=1,    B=0,    C=1,    D=1

1. A four-variable truth table and apply all combinations of input variables to the circuit and each time the logical state are noted –

The output for each possible input and its respective output

 

Input A	B	C	D	Output (Y)
0	0	0	0	90 mV
0	0	0	1	0.08 V
0	0	1	0	0.08 V
0	0	1	1	0.08 V
0	1	0	0	0.08 V
0	1	0	1	0.08 V
0	1	1	0	0.08 V
0	1	1	1	0.08 V
1	0	0	0	0.08 V
1	0	0	1	1.3 V
1	0	1	0	1.3 V
1	0	1	1	1.3 V
1	1	0	0	0.08 V
1	1	0	1	0.08 V
1	1	1	0	0.08 V
1	1	1	1	0.08 V

 

1. The circuit operation –

The Circuit operation

 

The circuit consist of A and B^— and B is passed through the inverter to get the inverted B. then the inverted B and A are passed to the AND gate. On the other path C and D are passed to the OR gate. The output of AND gate and output of OR gate is passed to the output AND gate to get the final output Y.

The final output will give High value only when (A is High and B is low) and either of C or D is High. This is clarified by the truth table, simulation, and k-map.

Opportunity for Distinction (D2) –

 

The all parts of Task 2 are completed.

1. Boolean expression is defined for the required operation.
2. The Sum of product is also determined.
3. The circuit is designed and simulated. The simulation results for high output are noted as waveform and all others values are noted in the truth table.
4. Four-variable truth table is made and applies all combinations of input variables to circuit and each time logical state are noted in the table.
5. The circuit operation is discussed and explained.

Opportunity of Merit (M2) –

 

The Karnaugh Maps to check the SOP found is equivalent to original Boolean expression.

The k-map,

 

0	0	0	0
0	0	0	0
0	0	0	0
0	1	1	1

 

 

 

TASK 3: (L04.2b & L04.3b)

1. Design of 4 bit asynchronous counter using JK flip flops to count between 2 and 9 –

 

State or Flow diagram,

The Sequence table –

 

Present State	Next State
0010	0011
0011	0100
0100	0101
0101	0110
0110	0111
0111	1000
1000	1001
1001	0010

 

The excitation table –

 

Present State	Next State	Flip Flop Input
		JD	KD	JC	KC	JB	KB	JA	KA
0000	0010	0	X	0	X	1	X	0	X
0001	0010	0	X	0	X	1	X	X	1
0010	0011	0	X	0	X	X	0	1	X
0011	0100	0	X	1	X	X	1	X	1
0100	0101	0	X	X	0	0	X	1	X
0101	0110	0	X	X	0	1	X	X	1
0110	0111	0	X	X	0	X	0	1	X
0111	1000	1	X	X	1	X	1	X	1
1000	1001	X	0	0	X	0	X	1	X
1001	0010	X	1	0	X	1	X	X	1
1010	0010	X	1	0	X	X	0	0	X
1011	0010	X	1	0	X	X	0	X	1
1100	0010	X	1	X	1	1	X	0	X
1101	0010	X	1	X	1	1	X	X	1
1110	0010	X	1	X	1	X	0	0	X
1111	0010	X	1	X	1	X	0	X	1

 

The Karnaugh maps –

 

The k-map for J_D –

0	0	0	0
0	0	1	0
X	X	X	X
X	X	X	X

 

The k-map for K_D –

X	X	X	X
X	X	X	X
1	1	1	1
0	1	1	1

 

The k-map for J_C –

0	0	1	0
X	X	X	X
X	X	X	X
0	0	0	0

 

 

The k-map for K_C –

X	X	X	X
0	0	1	0
X	X	X	X
1	1	1	1

 

The k-map for J_B –

1	1	X	X
0	1	X	X
1	1	X	X
0	1	X	X

 

The k-map for K_B –

X	X	1	0
X	X	1	0
X	X	0	0
X	X	0	0

 

The k-map for J_A –

0	X	X	1
1	X	X	1
0	X	X	0
1	X	X	0

 

The k-map for K_A –

X	1	1	X
X	1	1	X
X	1	1	X
X	X	1	X

1. The circuit simulation of sequence counter –

 

The sequence counter

 

The output of the above sequence detector

 

Clock	Present state	Next state
1	0000	0010
0	0010	0010
1	0010	0011
0	0011	0011
1	0011	0100
0	0100	0100
1	0101	0110
0	0110	0110
1	0110	0111
0	0111	0111
1	0111	1000
0	1000	1000
1	1000	1001
0	1001	1001
1	1001	0010
0	0010	0010
1	0010	0011
0	0011	0011

 

Opportunity for Merit (M3) –

The report is produces as shown in this task or work.

Opportunity for Distinction (D2)

The circuit is design and demonstrated with the simulation circuit and its output.

 

Bibliography

121/D, D. (2000, Jan). LS TTL Data. Retrieved from Rev. 6: http://ecee.colorado.edu/~mcclurel/ON_Semiconductor_LSTTL_Data_DL121-D.pdf

Instruments, T. (2002, Sept). HCMOS Design Considerations. Retrieved from SCLA007A: http://www.ti.com/lit/an/scla007a/scla007a.pdf

Maini, A. K. (2007). Digital Electronics : Principles, Devices and Apllications. John Wiley & Sons.